1. Field of the Invention
The present invention relates to data output circuits, particularly to a data output circuit employed as a data output buffer of a semiconductor memory device.
2. Description of the Background Art
As to data output from a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), the potential difference generated by the charge stored in a memory cell corresponding to the stored information is amplified by a sense amplifier or the like and is transmitted through data lines such as bit lines, I/O lines and the like to be subjected to a buffer process at the last stage for output to a data terminal. The transient current handled by the data output circuit is great during this operation. Latchup easily occurs if a P type MOS transistor is used at the output stage. Therefore, the transistor charging/discharging the data terminal is generally formed of an N type MOS transistor.
FIG. 21 is a block diagram showing a structure of a data output circuit 500 which is one example of the conventional art employed in a semiconductor memory device.
Data output circuit 500 outputs to a data terminal 510 digital data of the two states of a high level (simply referred to as H level hereinafter) and a low level (simply referred to as L level hereinafter). The potential level of data output terminal 510 is set to an external power supply potential Vdd when data output of an H level is designated, and set to a ground potential Vss when data output of an L level is designated.
Data output circuit 500 includes an output buffer 580 to supply external power supply potential Vdd or ground potential Vss to data terminal 510.
Output buffer 580 includes a pull up transistor QNa electrically coupled between external power supply potential Vdd and data terminal 510, having a gate coupled to a node Nb to output data of an H level, and a pull down transistor QNb electrically coupled between ground potential Vss and data terminal 510, and having a gate coupled to a node Nc to output data of an L level.
Data output circuit 500 further includes an H level data output control circuit 110 providing to node Nb a boosted potential that allows pull up transistor QNa to attain a deep ON state when H level data output is designated, an L level data output control circuit 140 supplying to node Nc a potential to turn pull down transistor QNb on when L level data output is designated, and an output potential retain circuit 160 to maintain the potential level of node Nb at a level of at least a constant value when H level data is output.
H level data output control circuit 110 includes a boosting circuit 120 responsive to control signals .phi.1 and .phi.2 to output a boosted potential higher than an internal power supply potential Vcc to node Na when H level data is output, and a potential switch circuit 125 responsive to control signal .phi.2 to set the potential level of node Nb to either the potential level of node Na or ground potential Vss.
L level data output control circuit 140 includes a level conversion circuit 150 to execute level conversion of a control signal .phi.3, and an inverter 155 responsive to an output of level conversion circuit 150 to output either external power supply potential Vdd or ground potential Vss to node Nc.
Control signal .phi.2 is rendered active (L level) when output of H level data is designated. Control signal .phi.3 is rendered active (L level) when output of L level data is designated. Control signal .phi.1 is rendered active (H level) to activate boosting circuit 120 prior to the output of H level data.
According to the above structure, boosted potential (&gt;Vdd) from boosting circuit 120 is output to node Nb whereas ground potential Vss is output to node Nc in an H level data output operation. Therefore, pull up transistor QNa attains a deep ON state, and pull down transistor QNb is turned off. As a result, data terminal 510 is charged to the level of external power supply potential Vdd.
In an L level data output operation, the potential of node Nc is set to the level of external power supply potential Vdd, and the potential level of node Nb is set to ground potential Vss. In this case, pull down transistor QNb is turned on and pull up transistor QNa is turned off. Therefore, data terminal 510 is discharged by transistor QNb, so that the potential level thereof corresponds to ground potential Vss.
By controlling the gate potential of two N type MOS transistors corresponding to the pull up transistor and the pull down transistor forming output buffer 580, data of either an H or L level can be output to data terminal 510.
From the standpoint of ensuring transistor breakdown voltage corresponding to increase in the integration density of circuitry and from the standpoint of lowering power consumption postulating drive by batteries, the need arises for a semiconductor memory device to operate at a low voltage level. A lower operating voltage causes reduction in the current drivability of the N type MOS transistor. Increase in speed of the data output circuit has become a critical issue in accordance with the demand for reduction in the operating voltage level.
FIG. 22 is a sectional view of a structure of an output buffer 580 of conventional art.
Referring to FIG. 22, pull up transistor QNa and pull down transistor QNb included in an output buffer 580 are provided at a P type well 530 on a P type substrate region 520. Substrate potential Vsub is applied to P well 530 through a contact 532. Substrate potential Vsub is generally a negative potential from the standpoint of preventing latchup.
Pull up and pull down transistors QNa and QNb are provided at the common P type well 530. Pull up transistor QNa includes a gate electrode 534a connected to node Nb, an n channel region 538a connected to data terminal 510 and an n channel region 536a coupled to external power supply potential Vdd, corresponding to source/drain electrodes. Similarly, pull down transistor QNb includes a gate electrode 534b connected to node Nc, and an N channel region 538b coupled to ground potential Vss and an N channel region 536b connected to data terminal 510, corresponding to source/drain electrodes.
In the conventional structure shown in FIG. 22, the charging speed of data terminal 510 by pull up transistor QNa in the output operation of H level data has become an issue.
In an N type MOS transistor, the substrate effect occurs according to the level difference between the source potential (potential level of data terminal 510 for pull up transistor QNa) and the substrate potential (potential level of P type well 530 for pull up transistor QNa) to result in a larger of threshold voltage Vth of the transistor. Therefore, when charging of data terminal 510 is initiated in an H level data output operation, the current drivability of transistor QNa is degraded due to the substrate effect caused by the boost of the source potential. There was a problem that data terminal 510 cannot be charged speedily depending upon reduction in the source-drain current. In order to increase the current drivability to speed up H level data output under such circumstances, a transistor of a large size must be provided as pull up transistor QNa. This will induce increase of the layout area.
In an H level data output operation, the gate potential of pull up transistor QNa, i.e. the potential level of node Nb must be boosted sufficiently. It has become difficult to obtain a sufficient boosted level by boosting circuit 120 in the case of operation at a low voltage. A boosting circuit includes a capacitor for boosting in order to store charge used for boosting. When this capacitor is formed of an MOS capacitor, the usage efficiency of the capacitance of the boosting capacitor is degraded since the effect of threshold voltage Vth becomes greater in accordance with reduction of the voltage level. This causes the aforementioned problem.